1. Field of the Invention
The present invention relates to a manufacturing process of semiconductor devices, and more specifically to an etching method, a gate etching method, and a method of manufacturing a semiconductor device.
2. Description of the Related Art
The demands for higher-speed and power-thriftier semiconductor devices are promoting finer design rules of semiconductor devices steady. Dimensional control values for each step have been often set approximately at actual dimensions ±10% heretofore. However, as the design rules become finer remarkably, required manufacturing accuracies become stricter.
Particularly to a gate manufacturing step, especially strict requests have been made because the accuracies in the gate manufacturing step are linked to the performance of transistors and consequently associated with the ability of all the LSIs to a large extent. The gate size of a device, which has been developed heretofore, is approximately 50-100 nm. Considering a control range of the gate to be ±10%, a dimensional control value is expressed as ±5-10 nm. The higher the accuracy is, the better the accuracy is, of course.
Further, it is difficult to achieve currently required dimensions only by the lithography. Accordingly, techniques of slimming (reducing in width) a resist pattern by plasma etching before processing a gate material are commonly adopted. The techniques can be roughly classified as methods by which only a resist is slimmed; or methods by which a resist and a resist-underlying films, i.e. an organic film located under the resist, are slimmed simultaneously. In a method of slimming only a resist, a conventional ashing apparatus is utilized to carry out isotropic etching using oxygen (O2) plasma. However, the method has difficulty in addressing a thinner resist because the resist is etched not only from the side but also from above. Therefore, a method of simultaneously slimming a resist and an organic film located under the resist mainly has been often used as disclosed in Japanese unexamined published patent application JP-A-09-237777.
In general, it is a custom in many etching processes to carry out dummy discharge using a Si-substrate before plasma etching to improve the reproducibility and stability of the processes. Further, depending on a plasma etching system, cleaning discharge for cleaning within the etching system for each etching process can be performed.
Because a gate-slimming step by plasma etching is an important step influencing device characteristics, both the cleaning discharge and dummy discharge using a Si-substrate are often carried out.
It is also proposed to etch a dummy wafer, which has the same characteristics as those of a semiconductor wafer to be etched, by plasma etching in order to ensure stable states of etching characteristics immediately after cleaning discharge, as disclosed in Japanese unexamined published patent application JP-A-06-084851.
However, it has been understood that only the cleaning discharge and the dummy discharge using a Si-substrate can not address the requirements for dimensional accuracies, which are becoming increasingly stricter, because of difficulties in reproducibility and stability thereof in the case of using the foregoing method of slimming process.
FIG. 7 is a graph for explaining problems in the related art, in which three arbitrary isolated patterns are indicated by measurement points A, B, and C, and the horizontal and vertical axes represent numbers of the processing order and conversion differences (=a lithographic size minus an etching size) respectively.
The conversion difference is a sum of dimensional differences when slimming a resist-underlying film and when processing a gate material under the resist-underlying film. The presence of variations in the conversion difference means that conversion differences in etching change actual sizes widely even if lithographic sizes are precisely equivalent.
As a result, a dimensional accuracy becomes lower and variations in gate size arise even in the same lot, whereby the characteristics of transistors widely change from wafer to wafer.
Further, in the case where discharge is carried out using a dummy wafer having the same characteristics as those of a wafer to be etched, it is utilized that depositing reaction products, which are composed of the same components as those of a wafer to be etched, on the inside of an etching system causes etching characteristics to be moved into stable regions thereof.
In this case, it is necessary to remove only reaction products of a resist as contaminations by carrying out plasma cleaning because reaction products of the resist are deposited on the inside of the etching system when the dummy wafer has a resist pattern formed thereon.